16-bit CPU
Single-cycle CPU designed with Verilog
Background
In my sophomore year of college, I took a digital systems class where everyone designed a 16-bit CPU over the course of the semester. We designed the CPU in Quartus using Verilog, tested it on an FPGA board, and wrote reports about it at various milestones. The full CPU consists of an ALU, register file, data memory, instruction memory, and control unit.
Though there were many reports we had to write over the course of the project, I've opted to include report LE C.3 here since it involved the least starter code provided by the professors, whereas later assignments involving the instruction memory and control unit had a greater ratio of starter code relative to the code I wrote.
Most of the Verilog I wrote can be found at lines 206 and below, where the ALU and register transfer system are defined.